The present invention relates to a semiconductor device capable to being turned on and off by an insulated gate electrode, and, in particular, to a complex semiconductor device having a reduced resistance loss in the on state and being particularly suitable for developing a high breakdown voltage or allowing a large current.
Due to requirements of high performance of power transducers included in inverter systems, it has been desired to develop a high-speed semiconductor switching device attended with a reduced loss. Recently, as a semiconductor device satisfying such a requirement, an insulated gate bipolar transistor (IGBT) has attracted attention. The IGBT has, when compared with a metal insulator semiconductor field effect transistor (MISFET), features of a decreased on-state voltage. Moreover, as compared with devices of a current control type such as a GTO thyristor, the IGBT has certain important advantages. For example, it has a higher operation speed and its gate circuit is simple and can be implemented in a compact structure. Consequently, centered on an inverter of a relatively small capacity, the application range thereof is expanding.
Such an IGBT has been described, for example, in pages 220 to 225 of the Proceedings of 1991 International Symposium on Power Semiconductor Devices & ICs, Tokyo. FIG. 26 shows a schematic cross-sectional configuration of such an IGBT. In the diagram, numeral 400 indicates an n.sup.- -type layer adjacent to a principal surface 411, numeral 401 denotes an n.sup.- -type layer which is adjacent to the n.sup.- -type layer 400 and which has an impurity concentration higher than that of the layer 400, numeral 402 designates a p.sup.+ -type layer adjacent to the n.sup.- -type layer 401 and a principal surface 412, numeral 403 stands for a p-type layer which extends from the principal surface 411 into the n.sup.- -type layer 400 and which has an impurity concentration higher than that of the layer 400, numeral 404 indicates an n.sup.+ -type layer which extends from the principal surface 411 into the p-type layer 403 and which has an impurity concentration higher than that of the layer 403, numeral 405 denotes a cathode electrode which is brought into contact with the n.sup.+ -type layer 404 and the p-type 403 in the principal surface 411, a numeral 406 designates an anode electrode being brought into contact with the p.sup.+ -type layer 402 in the principal surface 412, and numeral 407 stands for an insulated gate electrode formed via an insulation layer 408 at least on the p-type layer 403 on the principal surface 411. The semiconductor device includes a pnp transistor (Q.sub.1) including the p.sup.+ -type layer 402, the n.sup.- -type layer 400, and the p-type layer 403; an npn transistor (Q.sub.2) including the n.sup.- -type layer 400, the p-type layer 403, and the n.sup.+ -type layer 404; and an n-channel MISFET (M.sub.1) including the insulated gate electrode 407, the n.sup.+ -type layer 404, the p-type layer 403, and the n.sup.- -type layer 400. Ordinarily, since the p-type layer 403 is designed to have a sufficiently small lateral resistance r, the npn transistor (Q.sub.2) does not have the opportunity to operate. Namely, the semiconductor above can be regarded as a complex of an MISFET and a pnp transistor. FIG. 27 shows an equivalent circuit of the semiconductor device of FIG. 26. Next, the operation principle will be described by reference to FIGS. 26 and 27.
First, to turn the semiconductor device on, a negative potential and a positive potential are applied respectively to the cathode electrode 405 and the anode electrode 406 such that the insulated gate electrode 407 is applied with a potential which is larger in terms of positive potential than that of the cathode electrode 405. Resultantly, on the surface of the p-type layer 403 below the insulated gate electrode 407, there is formed an inversion layer (channel) such that a short circuit is established between the n.sup.+ -type layer 404 and the n.sup.- -type layer 400 to turn the n-channel MISFET (M.sub.1) on. As a result, electrons (MIS current) injected from the cathode electrode 405 via the MISFET (M.sub.1) pass through the n.sup.- -type layer 400 to flow into the p.sup.+ -type layer 402, thereby injecting holes from the p.sup.+ -type layer 402 into the n.sup.- -type layer 400. The carriers are consequently accumulated to cause a conductivity modulation in the n.sup.- -type layer 400 so as to lower the resistance R of the n.sup.- -type layer 400, which sets the semiconductor device to the on state. Since the lateral resistance r of the p-type layer 403 is designed to be sufficiently small, a parasitic thyristor including the n.sup.+ -type layer 404, the p-type layer 403, the n.sup.- -type layer 400, and the p.sup.+ -type layer 402 (including Q.sub.1 and Q.sub.2) cannot be easily operated.
On the other hand, to turn the semiconductor device off, the potential of the insulated gate electrode 407 is set to be equal to or lower than that of the cathode electrode 405 to extinguish the inversion layer on the surface of the p-type layer 403 below the electrode 407 such that injection of electrons from the n.sup.+ -type layer 404 is interrupted. Resultantly, injection of holes from the p.sup.+ -type layer 402 is also stopped to set the semiconductor device to the off state.
In the IGBT above, since conductivity modulation occurs in the n.sup.- -type layer 400 due to injection of holes from the p.sup.+ -type layer 402, there can be characteristically developed an on-state voltage lower than that of the MISFET. Furthermore, since electrons from the n.sup.+ -type layer 404 serving as an emitter of the bipolar transistor are instantaneously injected or interrupted by the gate potential, a switching operation having a speed as high the speed of a MISFET can be carried out.
In addition, there has been recently proposed a new-type semiconductor device in which a thyristor is controlled by an insulated gate electrode. Such a device has been discussed, for example, in pages 256 to 260 of the Proceedings of 1992 International Symposium on Power Semiconductor Devices & ICs, Tokyo. FIG. 29 shows a semiconductor device described in conjunction with FIG. 1 of the above article. The device includes an n.sup.- -type layer 500 adjacent to a principal surface 511, an n-type layer 501 which is adjacent to the n.sup.- -type layer 500 and which has an impurity concentration higher than that of the n.sup.- -type layer 500, a p.sub.1.sup.+ -type layer 502 which is adjacent to the n-type layer 501 and a principal surface 512 and which has an impurity concentration higher than that of the n-type layer 501, a p.sub.2.sup.+ -type layer 503 which extends from the principal surface 511 into the n.sup.- -type layer 500 and which has an impurity concentration higher than that of the n.sup.- -type layer 500, a p.sup.- -type layer 504 which is adjacent to the p.sub.2.sup.+ -type layer 503, which extends from the principal surface 511 into the n.sup.- -type layer 500, and which has an impurity concentration between those respectively of the n.sup.- -type layer 500 and the p.sub.2.sup.+ -type layer 503, an n.sub.1.sup.+ -type layer 505 which extends from the principal surface 511 into the p.sub.2.sup.+ -type layer 503 and the p.sup.- -type layer 504 and which has an impurity concentration higher than that of the p.sub.2.sup.+ -type layer 503, an n.sub.2.sup.+ -type layer 506 which extends at a position apart from the n.sub.1.sup.+ -type layer 505 from the principal surface 511 into the p.sup.- -type layer 504 and which has an impurity concentration higher than that of the p.sup.- -type layer 504, a cathode electrode 509 being brought into contact with the n.sub.1.sup.+ -type layer 505 and the p.sub.2.sup.+ -type layer 503, an anode electrode 510 being brought into contact with the p.sub.1.sup.+ -type layer 502, a first insulated gate electrode G.sub.1 formed via an insulation layer on an exposed surface of the p.sup.- -type layer 504 exposed between the n.sub.1.sup.+ -type layer 505 and the n.sub.2.sup.+ -type layer 506, and a second insulated gate electrode G.sub.2 formed via an insulation layer on an exposed surface of the p.sup.- -type layer 504 exposed between the n.sup.- -type layer 500 and the n.sub.2.sup.+ -type layer 506. The semiconductor device has therein a thyristor including a pnp transistor (Q.sub.1) including the p.sub.1.sup.+ -type layer 502, the n.sup.- -type layer 500, and the p.sup.- -type layer 504 and an npn transistor (Q.sub.2) including the n.sup.- -type layer 500, the p.sup.- -type layer 504, and the n.sub.2.sup.+ -type layer 506. Moreover, the device has an n-channel MISFET (M.sub.1) including the first insulated gate electrode G.sub.1, the n.sub.1.sup.+ -type layer 505, the p.sup.- -type layer 504, and the n.sub.2.sup.+ -type layer 506 and an n-channel MISFET (M.sub.2) including the second insulated gate electrode G.sub.2, the n.sub.2.sup.+ -type layer 506, the p.sup.- -type layer 504, and the n.sup.- -type layer 500. In addition, as a parasitic element, there is included a parasitic thyristor including the n.sub.1.sup.+ -type layer 505, the p.sub.2.sup.+ -type layer 503, the n.sup.- -type layer 500, and p.sub.1.sup.+ -type layer 502.
FIG. 30 shows an equivalent circuit of the semiconductor device of FIG. 29. The operation principle will be next described by reference to FIGS. 29 and 30. First, to turn the semiconductor device on, a negative potential and a positive potential are applied respectively to the cathode electrode 509 and the anode electrode 510 such that each of the first and second insulated gate electrodes G.sub.1 and G.sub.2 is applied with a potential larger in terms of positive potential than that of the cathode electrode 509. Resultantly, an inversion layer is formed in the surface of the p.sup.- -type layer 504 below the first and second insulated gate electrodes G.sub.1 and G.sub.2 such that a short circuit is formed between the n.sub.1.sup.+ -type layer 505, n.sub.2.sup.+ -type layer 506, and the n.sup.- -type layer 500, thereby turning the n-channel MISFETs (M.sub.1 and M.sub.2). As a result, electrons (MIS current) injected from the cathode electrode 509 via the n-channel MISFETs (M.sub.1 and M.sub.2) pass the n.sup.- -type layer 500 to flow into the p.sub.1.sup.+ -type layer 502, and then holes are injected from the p.sub.1.sup.+ -type layer 502 into the n.sup.- -type layer 500. When the hole current reaches the p.sup.- -type layer 504 and flows into the cathode electrode 509, a potential difference appears due to a lateral resistance r.sub.2 of the p.sup.- -type layer 504. When the potential difference exceeds a diffusion potential between the p.sup.- -type layer 504 and the n.sub.2.sup.+ -type layer 506 (about 0.7 V for silicon at the room temperature), electrons are directly injected from the n.sub.2.sup.+ -type layer 506 into the n.sup.- -type layer 500 and hence the thyristor is ignited and the semiconductor device is set to the on state. In this connection, the resistor r.sub.1 is sufficiently small due to the high impurity concentration of the p.sub.2.sup.+ -type layer 503. Consequently, the parasitic thyristor including Q.sub.3 and Q.sub.4 cannot be easily turned on.
On the other hand, to turn the device off, the potential of the first and second insulated gate electrodes G.sub.1 and G.sub.2 is set to be equal to or less than that of the cathode electrode 509 such that the inversion layer in the surface of the p.sup.- -type layer 504 below the first and second insulated gate electrodes G.sub.1 and G.sub.2 is extinguished to interrupt injection of electrons from the n.sub.2.sup.+ -type layer 506. This resultantly interrupts injection of holes from the p.sub.1.sup.+ -type layer and hence the semiconductor is set to the off state.
The semiconductor device of this type has the following feature. Namely, thanks to the thyristor operation, electrons supplied from the cathode electrode 509 via the n-channel MISFET (M.sub.1) flow in a state where the electrons are extended in the lateral direction of the n.sub.2.sup.+ -type layer 506 and, hence, the on-state voltage (resistance loss) in the conductive state can be minimized as compared with the conventional IGBT. In addition, the device can be turned on and off respectively according to application and removal of the potential onto and from the insulated gate electrode. This leads to a feature that the gate circuit is quite simplified, similar to the case of the conventional IGBT.
Although they have increased in popularity, IGBTs suffer from certain problems. For example, due to the difficulty of obtaining a high breakdown voltage and a large current, IGBTs cannot be easily applied to an inverter having a large capacity. FIG. 28 shows simulation results of lines of current flow on the cathode side in the stationary on state of the IGBT. Electrons flowing from the cathode electrode 405 via the inversion layer (n channel) to the n.sup.- -type layer 400 are slightly extended in the lateral direction by an n.sup.+ -type accumulation layer formed in the surface of the n.sup.- -type layer 400 just below the gate electrode 407. However, according to influence from the large resistance of the n.sup.+ -type accumulation layer, the electrons cannot be fully extended. In consequence, in a position apart from the cathode electrode 405 (below the right insulated gate electrode in FIG. 26), the current does not easily blow and, hence, the on-state voltage becomes larger. On the other hand, in a region below the p-type layer 403, due to depletion caused by a potential drop in the n.sup.- -type layer 400, the current does not easily flow. This phenomenon is more remarkable when the impurity concentration of the n.sup.- -type layer 400 becomes lower to attain a higher breakdown voltage. Namely, for a higher breakdown voltage, the gate length is required to be elongated, which in turn results in deterioration of extension of the current flow in the lateral direction. In other words, the electron supply from the cathode side is decreased and the conductivity modulation effect is reduced. Consequently, when the breakdown voltage of the IGBT is increased, the on-state voltage becomes considerably higher, which leads to a problem of difficulty in increasing the capacity.
Moreover, the thyristor of the MIS gate type above is attended with a problem that the thyristor cannot be easily ignited. In the conventional device, as described above, when the device is turned on, an inversion layer is first formed in the surface of the p.sup.- -type layer 504 below the insulated gate electrodes G.sub.1 and G.sub.2 and then the n-channel MISFETs (M.sub.1 and M.sub.2) are turned on to form a short circuit between the n.sub.1.sup.+ -type layer 505, the n.sub.2.sup.+ -type layer 506, and the n.sup.- -type layer 500. Resultantly, as can be seen from the equivalent circuit of FIG. 30, electrons (MIS current) injected from the cathode electrode 509 into the n.sup.- -type layer 500 are required to pass the inversion layers (channels) of the two MISFETs M.sub.1 and M.sub.2, and, hence, the electron current is limited due to the channel resistance. In consequence, since the hole current from the p.sub.1.sup.+ -type layer 502 is small, the thyristor is not easily ignited. To prevent this phenomenon, there may be employed a method of increasing the area (channel width) of M.sub.2 or decreasing the area of the n.sub.2.sup.+ -type layer 506. This, however, means that the area of the thyristor through which the main current is passed is minimized in the overall semiconductor device. Consequently, the resistance loss (on-state voltage) in the conductive state is increased, which leads to a problem similar to that of the conventional IGBT.
Moreover, in the the MIS gate-type thyristor, the p.sup.- -type layer 504 is connected via the p.sup.+ -type layer 503 to the cathode electrode; consequently, it is difficult to ignite the thyristor. Namely, the voltage drop caused by the lateral resistance r.sub.2 of the p.sup.- -type layer occurs particularly in the vicinity of the cathode electrode and is hence small. In consequence, the thyristor is not ignited in the region. As a result, there arises a problem that only a portion of the thyristor is ignited, and, hence, the on-state voltage is increased.